Towards a Dependable True Random Number Generator With Self-Repair Capabilities

Many secure-critical systems rely on true random number generators that must guarantee their operational functionality during its intended life. To this end, these generators are subject to intensive online testing in order to discover any flaws in their operation. The dependability of the different blocks that compose the system is crucial to guarantee the security. In this paper, we provide some general guidelines for designers to create more dependable true random number generators. In addition, a case of study where the system dependability has been improved is presented.This work was supported in part by ICT COST Action under Grant IC1204 and in part by the Spanish Ministry of Economy and Competitiveness under Grant ESP2015-68245-C4-1-P

Partial TMR in FPGAs Using Approximate Logic Circuits

TMR is a very effective technique to mitigate SEU effects in FPGAs, but it is often expensive in terms of FPGA resource utilization and power consumption. For certain applications, Partial TMR can be used to trade off the reliability with the cost of mitigation. In this work we propose a new approach to build Partial TMR circuits for FPGAs using approximate logic circuits. This approach is scalable, with a fine granularity, and can provide a flexible balance between reliability and overheads. The proposed approach has been validated by the results of fault injection experiments and proton irradiation campaigns.This work was supported in part by the Spanish Ministry of Economy and Competitiveness under contract ESP2015-68245-C4-1-P

A Hybrid Fault-Tolerant LEON3 Soft Core Processor Implemented in Low-End SRAM FPGA

In this work we implemented a hybrid fault-tolerant LEON3 soft-core processor in a low-end FPGA (Artix-7) and evaluated its error detection capabilities through neutron irradiation and fault injection in an incremental manner. The error mitigation approach combines the use of SEC/DED codes for memories, a hardware monitor to detect control-flow errors, software-based techniques to detect data errors and configuration memory scrubbing with repair to avoid error accumulation. The proposed solution can significantly improve fault tolerance and can be fully embedded in a low-end FPGA, with reduced overhead and low intrusiveness

Autonomous fault emulation: a new FPGA-based acceleration system for hardness evaluation

The appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past.This work was supported by the Directorate of Research of Madrid Community Government, Spain (Code 07/0052/2003 2) and by the European Commission and Spanish Government under MEDEA+ Project (PARACHUTE-2A701) and PROFIT Project (CIRCE-FIT-330100-2005-60)

Extensive SEU impact analysis of a PIC microprocessor for selective hardening

In order to increase the robustness of a circuit against SEUs, fault injection is commonly used to locate weak areas. autonomous emulation is a very powerful tool to locate these areas by executing huge fault injection campaigns. In this work, fault injection has been extensively applied to a PIC18 microprocessor, while executing three different workloads. A 80 million fault campaign has been performed, and results show that a failure rate lower than 1% can be obtained by hardening a 24% of the circuit flip-flops, for the given applications

Error Detection and Mitigation of Data-Intensive Microprocessor Applications Using SIMD and Trace Monitoring

This article proposes a software error mitigation approach that uses the single instruction multiple data (SIMD) coprocessor to accelerate computation over redundant data. In addition, an external IP connected to the microprocessor's trace interface is used to detect errors that are difficult to cover with software-implemented techniques. The proposed approach has been implemented in an ARM microprocessor, and an irradiation campaign with neutrons has been carried out at Los Alamos National Laboratory. Experimental results demonstrate the high error coverage (more than 99.9%) of the proposed approach. The neutron cross section of errors that were not corrected nor detected was reduced by more than three orders of magnitude

Error Mitigation Using Approximate Logic Circuits: A Comparison of Probabilistic and Evolutionary Approaches

Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very high area overhead, so partial redundancy is often used to reduce the overheads. Approximate logic circuits provide a general framework for optimized mitigation of errors arising from a broad class of failure mechanisms, including transient, intermittent, and permanent failures. However, generating an optimal redundant logic circuit that is able to mask the faults with the highest probability while minimizing the area overheads is a challenging problem. In this study, we propose and compare two new approaches to generate approximate logic circuits to be used in a TMR schema. The probabilistic approach approximates a circuit in a greedy manner based on a probabilistic estimation of the error. The evolutionary approach can provide radically different solutions that are hard to reach by other methods. By combining these two approaches, the solution space can be explored in depth. Experimental results demonstrate that the evolutionary approach can produce better solutions, but the probabilistic approach is close. On the other hand, these approaches provide much better scalability than other existing partial redundancy techniques.This work was supported by the Ministry of Economy and Competitiveness of Spain under project ESP2015-68245-C4-1-P, and by the Czech science foundation project GA16-17538S and the Ministry of Education, Youth and Sports of the Czech Republic from the National Programme of Sustainability (NPU II); project IT4Innovations excellence in science - LQ1602

The Use of Microprocessor Trace Infrastructures for Radiation-Induced Fault Diagnosis

This work proposes a methodology to diagnoseradiation-induced faults in a microprocessor using the hardwaretrace infrastructure. The diagnosis capabilities of this approachare demonstrated for an ARM microprocessor under neutronand proton irradiation campaigns. The experimental resultsdemonstrate that the execution status in the precise moment thatthe error occurred can be reconstructed, so that error diagnosiscan be achieved

A true random number generator based on gait data for the Internet of You

The Internet of Things (IoT) is more and more a reality, and every day the number of connected objects increases. The growth is practically exponential -there are currently about 8 billion and expected to reach 21 billion in 2025. The applications of these devices are very diverse and range from home automation, through traffic monitoring or pollution, to sensors to monitor our health or improve our performance. While the potential of their applications seems to be unlimited, the cyber-security of these devices and their communications is critical for a flourishing deployment. Random Number Generators (RNGs) are essential to many security tasks such as seeds for key-generation or nonces used in authentication protocols. Till now, True Random Number Generators (TRNGs) are mainly based on physical phenomena, but there is a new trend that uses signals from our body (e.g., electrocardiograms) as an entropy source. Inspired by the last wave, we propose a new TRNG based on gait data (six 3-axis gyroscopes and accelerometers sensors over the subjects). We test both the quality of the entropic source (NIST SP800-90B) and the quality of the random bits generated (ENT, DIEHARDER and NIST 800-22). From this in-depth analysis, we can conclude that: 1) the gait data is a good source of entropy for random bit generation; 2) our proposed TRNG outputs bits that behave like a random variable. All this confirms the feasibility and the excellent properties of the proposed generator.This work was supported in part by the Spanish Ministry of Economy and Competitiveness under Contract ESP2015-68245-C4-1-P, in part by the Leonardo Grant for Researchers and Cultural Creators, BBVA Foundation under Grant P2019-CARDIOSEC, and in part bythe Comunidad de Madrid, Spain, under Project CYNAMON (P2018/TCS-4566), co-financed by the European Structural Funds (ESF andFEDER